Most of semiconductor devices such as a DRAM (Dynamic Random Access Memory) or the like are of a type which operates in synchronism with a clock signal. In such a synchronous semiconductor device, when a frequency of the clock signal rises, consumed power of an input circuit that fetches an address signal or a command signal increases, and therefore various kinds of propositions for reducing the consumed power of the input circuit at a time of being inactive have been made (see Japanese Patent Application Laid-open Nos. H7-230688, H11-16349, and 2007-12128).
For example, Japanese Patent Application Laid-open No. H7-230688 describes a method in which in response to a chip select signal being inactive, an operation of an input buffer that receives the address signal or the command signal is stopped. More specifically, when the chip select signal is inactivated, a bias current of a differential amplifier circuit configuring the input buffer is cut, and the consumed power thereby is reduced. However, when the bias current of the differential amplifier circuit is cut, a predetermined time is necessary to make the differential amplifier circuit operable again, and therefore, when the frequency of the clock signal is particularly high, adopting such a method is difficult.
Meanwhile, Japanese Patent Application Laid-open No. H11-16349 describes a method in which in response to a chip select signal being inactive, a supply itself of a clock signal for an internal circuit is stopped. However, when an internal clock signal is stopped, restoring the internal circuit takes time, and therefore, it is thought to be inappropriate to stop the clock signal itself in sequence with the chip select signal.
Further, Japanese Patent Application Laid-open No. 2007-12128 describes a method in which in response to a chip select signal being inactive, a clock signal supply to a latch circuit that latches an address signal or the like is stopped. However, between an input buffer and the latch circuit, there exist various kinds of circuits, such as a delay circuit, which adjust a timing. Therefore, even when an operation of the latch circuit is stopped, a charge/discharge current generated from an operation of the delay circuit or the like cannot be reduced.